The process of implementing a circuit design within a particular integrated circuit (IC), referred to as a target device, typically begins with an architecture description of the circuit design. This description can be specified in a hardware description language such as Verilog or VHDL. Most circuit designs have one or more timing requirements that must be observed. The timing requirements can be expressed within the programmatic description of the circuit design or as supplemental information or files accompanying the circuit design.
Electronic Design Automation (EDA) tools can process the circuit design and find an implementation for a given target device that meets the timing requirements. The EDA tool typically converts the HDL description of the circuit design into a gate-level representation of the circuit design. With respect to programmable logic device (PLD) type ICs, such as field programmable gate arrays, the gate level description can be technology mapped to vendor specific structures available within the target device. Elements of the circuit design are assigned to different components of the target device, e.g., lookup tables, flip-flops, and the like.
After technology mapping, delay information for interconnects of the circuit design can be calculated. The delay information for interconnects is effectively an estimation of signal propagation delays within the circuit. Because the circuit design has not yet been placed, this estimation of interconnect delays generally is not considered highly accurate.
The EDA tool then can place the technology mapped circuit design. The various elements of the circuit design, now associated with components of the target device, can be assigned to pre-fabricated sites, or locations, of the target device. The placement task generally can be guided by the delay information available. Connections of the circuit design can be routed to generate a routed circuit design.
Conventional EDA tools often have difficulty in processing signals of the circuit design that are distributed to a large number of load pins. It is often the case that these “high fanout signals” contribute to the failure of the EDA tool to determine a satisfactory implementation of the circuit design, e.g., an implementation that conforms to the established timing requirements.